Scan Insertion/Test and ATPG (Automatic test pattern generation)

Scan Test vs Boundary Scan Test

A scan test is used to test the internal logic (the chain uses the same clock as the design), whereas the boundary scan is used to test the external logic (the chain has its own clock).

Scan Test

The scan chain replaces the original storage elements (flip-flops/registers). This means after the scan chain insertion no additional flip-flops are used, but only some muxes (which consists of transistors) and in/outputs are added. To select which input is used as flip flop input the input signal “sc_en” is used. When it is set to one the chain is enabled and the inputs are taken from the chain, if it is zero the inputs are taken from the original logic. Furthermore, “sc_in” and “sc_out” are added, which build the input and the output of the chain.

In order that one does not have to build the chain by our own there is a tool provided by cadance named genus. It allows generating the scan chain in a .tcl scripted way. ⇒ Normally it takes all flip-flops found in the design and adds them to the chain. It is also possible to add observation test points manually. As in the example below, which adds the signal with the name “direction_ns” to the chain.

add_test_point -location direction_ns -type "observe_scan" -test_control test_mode -test_clock_pin clk


  • What does the following line mean:
set_attribute lp_clock_gating_test_signal scan_enable "/designs/$DESIGN"
  • Is it possible to add one observation test point to another clock when one changes the -test_clock_pin?
add_test_point -location direction_ns -type "observe_scan" -test_control test_mode -test_clock_pin clk
  • Lab 3.1 Question 29. I do not see that big difference? Calc direction overflow block seems nearly the same.

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