How does the AXI4-Lite VALID / READY handshake work?

Every AXI4-Lite channel uses the same handshake: the sender drives VALID together with the payload and the receiver drives READY. A transfer happens only at a rising ACLK edge where VALID and READY are both 1. The sender must not wait for READY before asserting VALID, and once VALID is high it must stay high with an unchanged payload until the handshake. The receiver may wait for VALID before asserting READY.

What are the five AXI4-Lite channels?

A write uses three channels: AW (write address), W (write data with WSTRB byte strobes) and B (write response BRESP). A read uses two channels: AR (read address) and R (read data RDATA together with RRESP). AW, W and AR are driven by the master; B and R are driven by the slave. Reads and writes are fully independent and may run in parallel.

What is the difference between SLVERR and DECERR in AXI?

SLVERR (2'b10) means the slave was reached but reports an error, for example a write to a read-only register. DECERR (2'b11) means no slave exists at that address and is usually generated by the interconnect default slave. In both cases all handshakes still complete normally; EXOKAY is not used in AXI4-Lite.

Why can an AXI4-Lite design deadlock?

A deadlock happens when a master waits for AWREADY before raising WVALID while the slave waits for both AWVALID and WVALID before raising AWREADY. The slave behaviour is allowed by the specification; the master breaks the rule that VALID must never wait for READY. AXI has no timeout, so the bus hangs until reset.

AXI4-Lite Explained: Handshakes, Writes, Reads, Errors, and State Machines

Post author:Matthias
Post published: October 30, 2026
Post category:FPGA
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$ axi4-lite --explain --cycle-by-cycle

AXI4-Lite explained: handshakes, writes, reads, errors and state machines

An interactive guide for people who have never used AXI. Each step loads a scenario into a small cycle-accurate simulator of one master and one register slave. Move through the clock edges and watch the five channels, the waveform, the state machines on both sides and the registers. The playground lets you change every delay and build your own transactions, including ones that break the rules.

AXI4-Lite Explained: VALID / READY Handshakes, Write and Read Channels, Byte Strobes, Error Responses and State Machines

Learn the AMBA AXI4-Lite protocol cycle by cycle with an interactive simulator of one master and one register slave: the five channels AW, W, B, AR and R, the VALID / READY handshake, wait states and back-pressure, address before data and data before address, WSTRB byte strobes, write-1-to-clear registers, BRESP and RRESP responses OKAY, SLVERR and DECERR, read latency, read / write ordering, back-to-back transactions, the AWREADY / WVALID deadlock, illegal VALID withdrawal, ARESETn reset behaviour and a full playground.

Tags: AMBA, ASIC, AXI, AXI4-Lite, Digital Design, FPGA, State Machine, Verilog, VHDL

AXI4-Lite Explained: VALID / READY Handshakes, Write and Read Channels, Byte Strobes, Error Responses and State Machines

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