AXI4-Lite Explained: Handshakes, Writes, Reads, Errors, and State Machines
Interactive cycle accurate AXI4 Lite simulator covering VALID READY handshakes, write and read channels, WSTRB byte strobes, SLVERR, DECERR, and FSMs.
I²C Explained: Open-Drain, START/STOP, Bits, ACK, Addressing, Stretching, and Arbitration
Interactive tick by tick I2C bus simulator covering open drain pull ups, START and STOP conditions, ACK and NACK, 7 bit addressing, and arbitration.
How Ethernet Works: From Plug In to TCP, Every Frame on the Wire
Interactive byte by byte guide to how Ethernet works from 1000BASE T PHY auto negotiation through DHCP, ARP, 802.1Q VLAN switching, IPv4 routing, and TCP.
Questa Wave Window Tips
Tips and keyboard shortcuts for navigating the QuestaSim wave window, placing delta cursors, and measuring signal switching speeds.
Analyzing Signals in QuestaSim Using TCL Commands and measure clock frequencies
Learn how to inspect signals, measure clock frequencies, and script automated waveform analysis in QuestaSim using TCL commands.
Timing Arcs
Understand timing arcs in digital logic, exploring how propagation delays and transition edges shape static timing in Vivado.
Vivado Timing analysis
Master Vivado timing analysis using TCL commands to query pins, cells, clocks, and calculate worst negative slack on FPGA paths.
Data Types
A comprehensive guide to VHDL data types, including std logic, signed arithmetic vectors, arrays, and custom enumerated types.
I/O Planning
Guidelines for efficient FPGA I/O planning, organizing package pin assignments, differential pairs, and bank voltages in Vivado.
VHDL Objects, Keywords, and Identifiers
A quick reference guide to VHDL keywords, reserved identifiers, and naming rules essential for writing compliant hardware models.
VHDL Design Units
Explore VHDL design units, examining how entity declarations and architecture bodies structure modular digital hardware.
VHDL Introduction
An introductory tutorial to VHDL, covering fundamental concepts of hardware description languages and digital circuit modeling.