Introduction
When working with digital designs in QuestaSim (ModelSim), understanding how to analyze signals programmatically using TCL commands is essential. This post will guide you through the basics of signal analysis and demonstrate how to create a useful clock frequency measurement utility.
Basic Signal Access in QuestaSim
Understanding Signal Paths
In QuestaSim, signals can be accessed in several equivalent ways:
sim:/design/instance/my_clock # Full path with dataset /design/instance/my_clock # Full path without dataset design/instance/my_clock # Relative path
The “sim:” prefix represents the current dataset name, which you can verify using:
dataset current # Returns "sim" for active simulation
Examining Signal Values
To check a signal’s value, use the examine
command:
examine design/instance/my_clock # Current value examine -time {1000 ns} design/instance/my_clock # Value at specific time
Signal Logging and Wave Window
An important note: When a signal is added to the Wave window using add wave
, it is automatically logged to the WLF (Wave Log Format) file. You don’t need to use the log
command separately for signals already in the Wave window.
Creating a Clock Frequency Analysis Tool
Let’s create a powerful utility to measure clock frequencies. Save this as clock_utils.tcl
:
############################################################################### # Clock Frequency Calculation Utility # # Description: # This procedure calculates the clock frequency by finding two consecutive # rising edges of a given signal starting from a specified time. # # Usage: # calculate_clock_frequency <start_time> <signal_path> # # Parameters: # - start_time: The time from which to start searching for rising edges (e.g., "1000ns") # - signal_path: Full path to the clock signal in the design # # Returns: # - Frequency in MHz # # Examples: # # Basic usage # set freq [calculate_clock_frequency 1000ns /design/instance/my_clock] # # # If you want to just print the frequency # calculate_clock_frequency 1000ns /design/instance/my_clock ############################################################################### # Time unit conversion helper proc convert_to_ns {time_str} { set time_str [string trim $time_str] array set unit_factors { "fs" 0.001 "ps" 1.0 "ns" 1000.0 "us" 1000000.0 "ms" 1000000000.0 "sec" 1000000000.0 } foreach {unit factor} [array get unit_factors] { if {[string match "*$unit" $time_str]} { set numeric_value [scan [string range $time_str 0 end-[string length $unit]] return [format } } return "${time_str}ns" } # Main frequency calculation procedure proc calculate_clock_frequency {start_time signal} { # Find first rising edge set first_time [lindex [lindex [searchlog -count 1 -rising $start_time $signal] 0] 0] # Find second rising edge set second_time [lindex [lindex [searchlog -count 2 -rising $start_time $signal] 0] 0] # Convert times to ns set first_time_ns [convert_to_ns $first_time] set second_time_ns [convert_to_ns $second_time] # Strip 'ns' and convert to numeric set first_numeric [scan [string range $first_time_ns 0 end-2] set second_numeric [scan [string range $second_time_ns 0 end-2] # Calculate period and frequency set period [expr {$second_numeric - $first_numeric}] set frequency [expr {1000.0 / $period}] puts "First Edge: $first_time_ns" puts "Second Edge: $second_time_ns" puts "Period: $period ns" puts "Frequency: [format return $frequency }
Understanding Key Commands
searchlog
Command:
searchlog -count 1 -rising $start_time $signal
-count 1
: Find first occurrence-rising
: Look for rising edge- Returns a nested list containing time and match count
- List Processing:
[lindex [lindex [...] 0] 0]
- Extracts time value from nested list structure
- First
lindex
gets outer list element - Second
lindex
gets inner time value
restart
Command:
- Resets simulation to time 0
- Reloads design elements that have changed
- Maintains current signal logging setup
Using the Utility
- Source the utility file in your simulation:
source clock_utils.tcl
- Calculate clock frequency:
calculate_clock_frequency 1000ns /design/instance/my_clock
Conclusion
This toolset provides a robust way to analyze clock signals in your QuestaSim simulations. By combining TCL’s powerful list processing with QuestaSim’s signal analysis commands, we can create sophisticated measurement utilities.
Remember:
- Signals in Wave window are automatically logged
- Use full paths for reliable signal access
- The current dataset (usually “sim:”) is optional in paths
- TCL’s list processing is key for handling QuestaSim command outputs
This approach to signal analysis can be extended to create more complex analysis tools for your specific needs.