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Clock Domain Crossing Explained: Synchronizers, Gray Code, and Async FIFOs

Learning path · all chaptersDigital track D6 of 7: Clock domain crossingD7 UVM verification →
$ cdc --explain --edge-by-edge

Clock domain crossing explained: metastability, synchronizers, Gray code, handshakes and asynchronous FIFOs

An interactive guide to moving signals safely between unrelated clocks in an FPGA. Each step loads a circuit into a small two-clock simulator that models setup/hold windows, metastable flip-flops, wire skew and asynchronous resets. Step edge by edge, watch flops go metastable and resolve, and see which method survives which situation. Every method comes with synthesizable VHDL and SystemVerilog, checked in real simulators, and with the timing constraints that belong to it.

Clock Domain Crossing Explained: Metastability, 2-FF Synchronizers, Gray Code and Async FIFOs

Trace asynchronous clock domain crossings edge by edge: setup/hold window violations, metastable settling and MTBF, 2-FF bit synchronizers, pulse/toggle handshakes, multi-bit bus skew vs Gray-coded async FIFOs, reset synchronization, and downloadable VHDL, SystemVerilog, XDC, and SDC RTL files.

Keyboard: ← / → previous / next event · [ / ] previous / next metastable or key event · Shift + ← / → previous / next step. The simulator is a teaching model: the setup/hold window (1 ns) and the resolution times are drawn far larger than in a real FPGA, where the window is some tens of picoseconds and τ a few to some tens of picoseconds; MTBF numbers in the calculator are illustrative, use your vendor's characterization. Metastable flops resolve to the value whose change came before the balance point of the window, a simplification of what is in reality a random outcome. The VHDL and SystemVerilog modules were simulated with GHDL 6.0.0 and Verilator 5.054 (self-checking testbench in the code card). Further reading: C. E. Cummings, “Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog” (SNUG 2008) and “Simulation and Synthesis Techniques for Asynchronous FIFO Design” (SNUG 2002); AMD UG974 (XPM CDC and FIFO macros), UG903 (constraints), UG906 (report_cdc); Intel Quartus Prime user guides (metastability analysis, timing constraints).

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