UVM, from the first transaction
One tiny adder. A complete verification environment. Follow an idea all the way from a sequence object to real pins, then back to a checked result.
UVM Verification Explained: Reusable SystemVerilog Architecture, Sequences, Agents, and Scoreboards
Step through a complete UVM testbench from DUT pin interfaces and virtual interface config_db lookup to uvm_sequence_item transactions, driver/sequencer TLM handshakes, monitor analysis ports, automated reference scoreboards, and downloadable Verilator SystemVerilog sources.
Two directions. One independent check.
Commands travel toward the DUT. Observations travel back toward the scoreboard. The monitor sees pins, not the sequence's intentions.
Check your mental model
The whole run, one event at a time
Every step of a complete run: elaboration, build, connect, run with eight transactions, check, report and final. This is a deterministic JavaScript teaching model, not an HDL simulator; its timing matches the downloaded testbench. The last four operand pairs are illustrative, because real random values depend on simulator and seed. Keyboard: ← / → step, Space plays.
Who is doing the work right now?
The highlighted block is the actor of the selected event; numbered badges follow one transaction. Click any block for its responsibility.
Timing: drive, capture, observe
Clock period 10 ns. Inputs drive on falling edges; the DUT uses nonblocking assignments at rising edges. The monitor waits 1 ns after a rising edge before reading the registered output. The cursor marks the selected event.
Observed transactions
| Item | Drive | Observe | a | b | Expected | Actual | Result |
|---|
Event journal
| Event | Time | Phase | Actor | Operation |
|---|
Small files. Real UVM classes.
These are the same files embedded in the download. Highlight a responsibility to locate its implementation.
Compilation is order-sensitive
UVM package → interface → DUT → testbench package → top module. Importing a package makes its declarations visible; it does not compile the file for you. The uvm_macros.svh include expands macros and is a separate preprocessing operation.
Objects, methods, macros, and syntax
Every API family used in this example is covered here, alongside common next-step tools. "Example" means used in the download; "Next step" means guidance, not an implemented feature.
A complete, downloadable starting point
The ZIP contains your DUT, interface, UVM classes, simulation top, run script, and README. It does not contain a simulator or the external UVM library. No network connection is needed to read this page or download the embedded files.
What was actually verified?
Normal DUT: 8 matches, 0 UVM errors, 0 UVM fatals, PASS at 182 ns. Deliberately broken DUT: 8 mismatches, FAIL, run script exit status 1. This is a real SystemVerilog run, separate from the browser model.
The no-DPI UVM library emits two library capability warnings. The verified build uses Verilator's external concatenated UVM reference package. Normal Accellera-source and Questa script modes are supplied but have not been executed here. See the README for exact dependencies and limitations.
Reproduce the verified setup
git clone --depth 1 --branch v5.054 https://github.com/verilator/verilator.git verilator-source export UVM_REFERENCE="$PWD/verilator-source/test_regress/t/uvm/uvm_pkg_all_v2020_3_2_nodpi.svh" cd uvm_example bash run.sh verilator # Prove the checker detects a broken DUT: BUG=1 bash run.sh verilator
Install Verilator 5.054 (or a suitably compatible recent release), make, a C++ compiler with coroutine support, and Z3 first. Extract the ZIP into a directory named uvm_example. Run these commands in Linux, macOS with compatible tools, or WSL, not directly in Windows PowerShell. Simulator installation is not performed by this page.
With an Accellera installation
unset UVM_REFERENCE export UVM_HOME=/absolute/path/to/uvm bash run.sh verilator # Or, with Questa tools installed and licensed: bash run.sh questa
Use a UVM version supported by your simulator. For a vendor-supplied precompiled UVM library, follow that vendor's compile/link instructions instead of compiling another copy. Current Verilator supports selected modern UVM versions; do not assume an old installation will run class-based UVM.
Expected first observations
36 ns 0 + 0 = 0 56 ns 2 + 3 = 5 76 ns 15 + 1 = 16 96 ns 15 + 15 = 30 ... four randomized transactions ... 182 ns PASS: 8 transactions checked
