What is the main difference between NOR Flash and EEPROM memory cells?

NOR Flash uses 1 transistor per cell (storage transistor only) with a shared p-well bulk across an entire sector, making it roughly 2x denser and cheaper per bit but requiring sector-wise erase. FLOTOX EEPROM uses 2 transistors per cell (a select transistor in series with a storage transistor), enabling individual byte-wise erase and rewrite without disturbing neighboring bytes.

Why does Flash memory erase in sectors while EEPROM erases a single byte?

In NOR Flash, erase pulls electrons out of the floating gate into the shared p-well bulk using Fowler-Nordheim tunneling (-9 V on word lines, +9 V on the p-well). Because all rows in a sector share the same isolated triple-well p-well, every byte in the sector is erased to 0xFF simultaneously. In FLOTOX EEPROM, erase pushes electrons into the floating gate via the byte word line (+20 V) while the select transistor isolates unselected rows, erasing only the selected byte.

How do Erase and Program physics differ between NOR Flash and FLOTOX EEPROM?

NOR Flash erases via Fowler-Nordheim tunneling out to the p-well and programs selected 0 bits via Channel Hot Electron (CHE) injection into the floating gate (9 V gate, 4.5 V drain). FLOTOX EEPROM uses bidirectional Fowler-Nordheim tunneling through an 8 nm tunnel window for both erase (electrons tunnel in at 20 V control gate) and program (electrons tunnel out at 20 V drain passed through a 22 V select gate).

What is the floating gate bit convention in Flash vs EEPROM?

Both memories return 0xFF after an erase operation, but use opposite charge conventions. In NOR Flash, an empty floating gate (low threshold voltage Vt ~ 2 V) conducts during a 5 V read and represents bit 1, while a charged floating gate (Vt ~ 7 V) blocks current and represents bit 0. In FLOTOX EEPROM, a charged floating gate (Vt ~ +4 V) represents bit 1, while an empty floating gate (Vt ~ -2 V) conducts at a 2 V read gate and represents bit 0.

Flash vs EEPROM – inside the floating-gate cell

Step through idle, erase, program and read for both memories side by side. Wire colours show voltages, purple floating gates hold electrons, and pink arrows show cell current.

Legend

Wire colour = voltage (hotter colour = higher voltage)

Symbols

NOR Flash vs FLOTOX EEPROM: How Floating-Gate Memory Cells Work

What is the difference between Flash and EEPROM? NOR Flash uses 1 floating-gate storage transistor per cell in a shared triple-well p-well sector, erasing whole sectors simultaneously via Fowler-Nordheim tunneling (-9 V word line, +9 V p-well) and programming selected 0 bits via Channel Hot Electron (CHE) injection (9 V word line, 4.5 V bit line). FLOTOX EEPROM uses 2 transistors per cell (a select transistor in series with a floating-gate storage transistor) on a grounded common p-substrate, erasing and programming individual bytes via bidirectional Fowler-Nordheim tunneling at 20 V across an 8 nm tunnel oxide window without disturbing neighboring bytes.

Changing just ONE byte (WL0 / byte 0 → 0x5A)

NOR Flash – sector-wise erase

Read the whole sector into RAM (save WL1 = 0x3C, and in a real chip thousands of other bytes)
Erase the whole sector → WL0 and WL1 = 0xFF
Program WL0 = 0x5A
Re-program WL1 = 0x3C (restore everything else)
Verify by reading

5 steps, and the other row is erased and rewritten (extra wear).

EEPROM – byte-wise erase

Erase byte 0 only → 0xFF
Program byte 0 = 0x5A
Verify by reading

3 steps. Byte 1 (0x3C) is never touched.

At a glance

	NOR Flash	FLOTOX EEPROM
Transistors per cell	1: storage transistor only	2: select transistor + storage transistor
Density / cost	About 2× denser and cheaper per bit	Larger cell and more expensive per bit
Erase unit	Sector / block (shared p-well)	Byte (shared word line)
Erase physics	F-N tunneling, e⁻ OUT into the p-well (WL −9 V, bulk +9 V)	F-N tunneling, e⁻ IN through the tunnel window (CG 20 V)
Program physics	Channel hot electrons IN (WL 9 V, BL 4.5 V, needs current)	F-N tunneling, e⁻ OUT (BL 20 V via select T)
Role of the bulk	Triple well: one p-well per sector, driven during erase	p-substrate common to all cells, always 0 V
Bit convention	Charged FG = 0, empty = 1	Charged FG = 1, empty = 0
Read: current means	1 (erased cell conducts)	0 (empty cell conducts)
Change 1 byte	Read the sector, erase the sector, then reprogram everything	Erase the byte, then program the byte
Typical use	Firmware, code, and large data	Configuration, calibration, and small parameters that change often