You are currently viewing MSE Project Work Part 2: Buck Boost Converter ASIC Tapeout and Silicon Testing

MSE Project Work Part 2: Buck Boost Converter ASIC Tapeout and Silicon Testing

Building directly on Part 1’s pre layout architecture, Part 2 documents the physical layout, foundry tapeout, packaging, and post silicon bench characterization of the Sonova hearing instrument Buck Boost converter ASIC fabricated in 0.35 um CMOS technology.

Interactive 4-Switch H-Bridge Buck-Boost Mode Explorer (0.35 Β΅m ASIC)
Post-Silicon

Explore how the 4 integrated power switches automatically transition between Step-Down (Buck), Buck-Boost, and Step-Up (Boost) as battery / USB input voltage varies against target output.

PHYSICAL LAYOUT, PACKAGING, AND SILICON CHARACTERIZATION

  • Low resistance power transistor layout sized for up to 200 mA output current paired with analog bias cores and digital serial control logic.
  • Custom test PCB hardware designed for simultaneous dual hearing device charging verification, thermal checks, and closed loop efficiency curves.
  • Measured silicon parameters compared directly against simulated pre layout and post layout expectations.

TAPEOUT AND CHARACTERIZATION REPORT (44 PAGES)

TEST BENCH AND CONVERTER SCHEMATIC

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