Fault Models

Stuck at fault

The stuck at fault model looks at every single node in the circuit and checks if it is stuck (a node is at a flip-flop, when one has redundant logic, for example to reduce glitches, it is possible to not detect a fault, therefore it is maybe necessary to add additional flip-flops). Each node can have three states:

  • normal
  • stuck at ‘0’ (faulty state)
  • stuck at ‘1’ (faulty state)

The Image below shows a stuck at ‘0’ fault of an “and” gate.


We assume that there is only one stuck at fault. ⇒ Single fault assumption. But it is possible that multiple faults may occur. To reduce the test time the number of test vectors can be reduced as one can see in the image below, only the green test vectors are needed to detect all stuck at faults (note in this way it is no longer possible to determine from where the error is coming):


Bridging Fault

In the bridging fault model, one assumes that there is a bridge between two wires and generates test vectors to detect this fault.

Delay Fault

They do not cause a logical error, but an error in timing. ⇒ Can be caused by high resistance of a connection ⇒ Might be detected when frequency of IC is increased.

IDDQ Fault

Quiescent current of digital CMOS circuit is very low. If one mosfet is defect (Resistive bridges, resistive opens, transistor gate oxide defects) the current consumption will be significantly higher ⇒ One knows the IC is defect.

DefectsPhisical problems that occur while fabricating chips.
FaultsAre ways to model how defects manifast at a certain level of abstraction.
ErrorsAre defiation in the obeservations that we can’t detect faults from

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