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Intro

We do verification to check if we indeed designed what we have asked for and to differentiate between intact circuits and circuits with a malfunction. The verification must be considered during the following three design phases:

• Specification (are not requirements)
  • Contains all the data needed for the designer, for example:
    • V_sup (min, typ, max)
    • I_sup (min, typ, max)
    • etc.
  • In the best case it is an mathematical description
• Design
  • In this phase already some test can be executed or special elements can be added to the design to allow easier testing.
  • In this phase, one differentiates the following verification strategies:
    • Dynamic Verification
      • Simulation
        • With a Simulation, one can do the following tests:
          • Functional tests (for example with test patterns)
          • parametric tests (check certain electrical characteristics, like power consumption)
      • Debugging
      • Apply Stimuli and observer response
        • Test Vector: Is a stimulus that is applied to the input
        • Test Pattern: Is a test Vector with the output included ==> one can also check if the output is correct
        • Test Set: Is a set of digital patterns
    • Static Verification
      • Timing
      • Design Rules
• Testing
  • Once the chip is there, one can do the following test:
    • Structural test (is like a functional test, but with less test patterns to increase the test speed), goal is to sort out bad circuits

Examples for products where the verification was not good enough can be found on the following page.

Rule of Ten

A wafer costs 10’000 CHF and more, which is not that much money in the industry. ==> When one detects an error there, it is not that expensive.

If one sees the error at chip level, after dicing and packaging it is 10 times more. In the table below, one sees the different steps for an Electronic Circuit Realization. If one detects an error one step later, it costs ten times more than it would have been in the previous step.