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VHDL Introduction

Introduction to VHDL

VHDL (VHSIC Hardware Description Language) is a powerful and versatile language used for describing digital systems and circuits. It plays a crucial role in modern digital design, particularly in the development of Field-Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs).

History of VHDL

  1. 1981: The United States Department of Defense initiated requirements for the VHSIC (Very High Speed Integrated Circuit) program
    1. Need: A language that describes the behavior of designs for both documentation and simulation
    2. Result: VHSIC Hardware Description Language (VHDL)
  2. 1984: Xilinx produced the first FPGA, paving the way for programmable logic devices
  3. 1985: IBM and Texas Instruments released their first version of VHDL
  4. 1987: VHDL was subsequently developed by IEEE and adopted as IEEE Standard 1076
  5. 1993, 2002, 2008: Further development and standardization of the language
  6. 2019: The latest revision, VHDL-2019, was released

VHDL Usage and Purpose

VHDL was primarily developed for hardware modeling and documentation purposes. The VHDL standard 1076 was comprehensive with respect to modeling but defined only broad parameters for synthesis. This allowed synthesis tool manufacturers flexibility in creating netlists (files containing basic logic elements and their interconnections).

  • Primary uses:
    • Hardware description and modeling
    • Simulation of digital systems
    • Synthesis of digital circuits
    • Documentation of hardware designs
  • Implications:
    • A given source code file can result in different netlists across various tools and target technologies
    • Hardware modules may not have a consistent and universal gate-level implementation

Key Characteristics of VHDL as a Language

  • Case Insensitivity:
    • Upper- and lower-case letters are treated the same
    • Enhances readability and reduces syntax errors
  • Strong Typing:
    • Every signal, component, and function must be defined before use
    • Size and type of target signal/variable must match with the left-hand side
    • Helps catch errors early in the design process
  • Concurrency:
    • Not sequential like traditional programming languages
    • Allows operations to run in parallel
    • Supports various concurrent statements, instantiations, and process statements
    • Reflects the parallel nature of hardware
  • Hierarchy and Partitioning:
    • Supports and encourages the use of hierarchy and partitioning
    • Enables modular design and reusability of components
  • Single Pass Compilation:
    • Everything must be defined before it can be used
    • Xilinx tools automatically order files properly for analysis

VHDL Compilation Process

There are four levels of processing that can take place for a VHDL hardware model, culminating in either execution (simulation) or synthesis:

  • 1. Analysis:
    • The design unit is checked for syntax errors
    • Once finalized, it is stored in the default library (e.g., xil_defaultfor Xilinx tools)
  • 2. Elaboration:
    • The design hierarchy is fleshed out
    • Unique copies of each submodule instance are created
    • Generics are expanded at this level
  • 3a. Execution (Simulation):
    • The model is simulated in discrete time steps
    • Driven primarily by events on signals that trigger related processes
    • Tools like Vivado Simulator are used for this purpose
  • 3b. Synthesis:
    • A netlist description of the logic is generated
    • Can be in an industry-standard or vendor-specific format
    • Tools like Vivado Synthesis are used for this purpose

Levels of Abstraction in VHDL

VHDL supports multiple levels of abstraction, allowing designers to describe hardware at various levels of detail:

  • Behavioral Level:
    • Describes a system by concurrent algorithms
    • Each algorithm itself is sequential
    • Uses higher levels of abstraction elements
    • No regard to the structural realization of the design
sum <= a + b after 3ns;
x1: while (sum > 15) loop
  ...
end loop x1;
  • Register-Transfer Logic (RTL) Level:
    • Specifies characteristics of circuits by operations and transfer of data between registers and combinatorial logic
    • RTL design contains timing possibilities of operations scheduled to occur at certain times
sum <= a + b;
  • Gate/Structural Level:
    • Characteristics of a system are described by logical links and their timing properties
    • Shows the instantiations of components and their connections
inst_1: mux21 PORT MAP
        (a0 => inp1,
         a1 => inp2,
         s => sel,
         y => temp1);

VHDL and FPGAs

While VHDL was originally intended for documentation and simulation of circuit designs, synthesis capabilities have become crucial, especially for FPGA design:

  • Synthesis:
    • Process of converting VHDL code to a collection of FPGA-specific primitives and connections
    • Primitives must be physically realizable on the target FPGA
  • Simulation:
    • Runs on a computer, not on actual hardware
    • Offers additional abstractions and capabilities not available in physical hardware
    • Example: wait for 12.031 ns; is possible in simulation but requires clock accuracy better than 1 THz in hardware

Setting VHDL-2008 in Vivado Design Suite

To use VHDL-2008 features in Xilinx Vivado, you need to explicitly set the VHDL version:

For Project mode, use the following command:

set_property FILE_TYPE { VHDL 2008 } [get_files .vhd]

For Non-Project Mode, use the following command:

read_vhdl -vhdl2008

Conclusion

VHDL has evolved from a documentation and simulation language to a crucial tool in digital design, particularly for FPGAs. Its strong typing, concurrency, and support for multiple abstraction levels make it well-suited for describing complex digital systems. As hardware design continues to advance, VHDL remains an essential skill for digital designers, enabling them to create sophisticated, efficient, and reliable digital circuits.

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