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VHDL Design Units

Any VHDL code is composed of design units, these design units are the basic units blocks of which all source code behavioural rtl or structural code is comprised. A design unit may be the entire file or there may be more than one design unit in a file. All design units are ultimately compiled into a library.

Vhdl code design units contains:

  • Library
    • Libraries are the repositories for commonly used items and are comprised of one or more compiled packages, these Libraries are created by IEEE, Vendors or Designers for their code reuse.
    • To use a library, declare it first with the keyword library and then specify which part / package of the library should be used. When one wants to use all the packages, then add the .ALL statement.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMBER_STD.ALL
  • Package
    • Package is used to store / encapsulate common declarations like type, subtype, constant, procedure, function that can be shared across two or more design units.
    • A package has two parts a package declaration (only function / procedure declarations are allowed) which is mandatory and a package body (describes behaviour of the function or a procedure if no of these elements are declared the package body must not be used.) which is optional, when no functions and procedures are used.
package <package name> is
  <package declarative items>
end [package] <package name>;
package body <package name> is
  <package body declarative items>
end [package body] <package name>;
  • Entity
    • Describes the interface between the behaviour of the module and the “calling” module / outside world
    • The top of every design hierarchy must be an entity
    • Entity is modelled using an entity declaration and zero / more architectures
    • The Entity declaration:
      • describes the external view of the entity
      • Specifies name of the entity being models
      • Lists the set of interface ports
    • The entity consists of two parts
      • Generics: Give a list of default values used to control the width of the ports / internal signals
      • Ports: Give a list of input, output, and bidirectional signals. Note: Only the signals listed in the port are available to the architecture
        • There are four types of ports allowed in VHDL
          • In: Describes the signals arriving into the module Used / read but cannot be assigned
          • Out: Describes the signals produced by the module Assigned but cannot be read
          • Inout: Describes the bidirectional signals that can be used or modified
          • Buffered: Can be assigned but cannot be read internal to the module
entity <entity name> is
  <generic declarative area>
  <port declarative area>
end [entity] [<entity name>];
  • Architecture
    • Architecture describes the behaviour of the module and contains an internal description of the entity used to implement a design
    • VHDL allows infinite architectures of an entity if names are unique in the target library
    • Vivado synthesis allows multiple architectures if they are in different files and are analysed separately into target library; ensures that required architecture is enabled
architecture <architecture name> of <entity name> is
    <architecture declarative area (what is beeing used in the architecture signal constant component type subtype)>
  begin
    <architecture functional area (describe the behaviour of the module)>
  end [architecture ] [<architecture name>];
  • Configuration
    • Specifies the binding of one architecture body with the entity
    • Specifies the bindings of components used in the selected architecture body to the entity
    • Entity can have any number of different configurations
configuration <configuration name> of <entity name> is 
  <declartions>
  <block configuration>
end [configuration] [configuration name];

Typical VHDL “Module”

Typical VHDL Module:

  • Consists of three basic design units library, entity, and architecture design units
  • Member of design hierarchy
  • Performs a single idea / task
  • A small top-level VHDL module is made up of instantiated lower-level modules
  • Module should have defined interface, behaviour, and target performance
  • Project should have defined performance and connection to the outside

An example can be found below:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMBER_STD.ALL;
entity this_module is
  [<generic declaration>]
  [<port declaration>]
end entity this_module;
architecture BEH of this_module is
    <architecture declaration area>
  begin
    <architecture function descriptioni>
  end architecture BEH

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