A data type is a name associated with a set of values and a set of operations. Connected data objects in VHDL must be of the same type, because VHDL is a strongly typed langauge.
Scalar Data Types
Scalar data types in VDHL represent single values.
- bit
- Takes values ‘0’ & ‘1’
- should not be used any more instead one should use std_logic.
- boolean
- Takes values True and False
- Often used in test benches and behavioural modelling.
- synthesizeable
- std_logic
- Can have the following values (same as std_ulogic)
- ‘U’ Uninitialized
- ‘X’ Forcing Unknown
- ‘0’ Forcing zero
- ‘1’ Forcing one
- ‘Z’ High Impedance
- ‘W’ Weak unknown
- ‘L’ Weak zero
- ‘H’ Weak one
- ‘-‘ don’t care
- defined in the package
- is resolved whereas std_ulogic is unresolved(when two or more signals are driving another signal the output is not defined ⇒ unresolved) ⇒ std_ulogic throws an error if the signal is driffen twice whereas std_logic does not. ==> std_logic must be used for three state signals.
- Can have the following values (same as std_ulogic)
U | X | 0 | 1 | z | w | L | H | - | ||
---|---|---|---|---|---|---|---|---|---|---|
uninitialized unknown | U | U | U | U | U | U | U | U | U | U |
forcing low | 0 | U | X | 0 | x | 0 | 0 | 0 | 0 | x |
forcing high | 1 | U | x | x | 1 | 1 | 1 | 1 | 1 | x |
high impedance | z | U | x | 0 | 1 | z | w | L | H | x |
weak unknown | w | U | x | 0 | 1 | w | w | w | w | x |
weak low | L | U | x | 0 | 1 | L | w | L | w | x |
weak high | H | U | x | 0 | 1 | H | w | w | H | x |
Don't Care | - | U | x | x | x | x | x | x | x | x |
- integer
- has the range of -2^31+1 to 2^31-1
- comparisions are possible
- <
- >
- >=
- <=
- =
- /=
- real
- allows use of floating-point values
- has a range of 1e38 to -1e38
- character & strings
- are synthesizeable
- example constant MY_CHAR 🙂 ‘Q’
- once the string size is defined it can not be changed the old values will stay in the string when a new string is written.
- example constant msg: string(1 to 10) := “setup time”
- physical
- the only pre defined physical type is time.
- generally not synthesizable
- example constant TPD : time := 3ns;
- enumerated
- sdfg
Data Type Conversion
Casting
- Used to move from sdt_logic_vector –> signed and unsigned types
- Tpye cast between sdt_logic_vector and signed/unsigned can be used as long as the original and destination signals have the same bit width.
signal ex1 : sdt_logic_vector(3 downto 0); signal ex2 : signed(3 downto 0); signal ex3: unsigned(3 downto 0); ex2 <= signed(ex1); ex3 <= unsigned(ex1); ex1 <= std_logic_vector(ex2);
Conversion
- Used to move from signed and unsigned –> integer type
- Function from integer to signed/unsigned includes a specification of the intended bit width
signal ex1 : signed(3 downto 0); signal ex2 : integer; ex1 <= to_signed(ex2, ex1'length); ex2 <= to_integer(ex1);
Insert Conversion Table here!
Types & Subtypes
Types
- Type defines a set of values
- STD package defines a collection of types
- New type can be created using enumeration, arrays, records, etc.
type mem_array is array (integer range 0 to 1023) of std_logic_vector(15 downto 0);
Subtypes
- Provide a mechanism for limiting the range of a type
- Used in simulation to do boundary checking
subtype <new subtype name> is <type or subtype name>; subtype ROM_MEMORY_RANGE is integer 0 to 255;