VHDL Introduction


  1. 1981 United States Department of Defence initiated requirements for VHSIC (Very High speed integrated circuit) program
    1. Need – A language that describes the behaviour of the designs for both documentation & simulation
    2. Result – VHSIC Hardware Description Language (VHDL)
  2. 1984 Xilinx produced the first FPGA
  3. 1985 IBM and Texas Instruments released their first version of VHDL
  4. 1987 Subsequently developed by IEEE & adopted in the form of IEEE Standard 1076
  5. 1993, 2002 2008 further development of the language

VHDL Usage

It was mainly developed for hardware modelling and documentation purpose. ⇒ VHDL standard 1076 was exhaustive with respect to modelling, but defined only broad parameters for synthesis. This allowed synthesis tool manufacturers to create a netlist (a file that contains basic logic elements and how they are interconnected) in any way they wish. Thus, for a given source code file there can be many different netlists created. ⇒ A given hardware module does not necessarily lend itself to a consistent and universal gate-level implementation across various tools and target technologies.

VHDL as a Language

  • NOT Case Sensitive
    • Upper- and lower-case letters are treated as same
  • Strongly Typed Language
    • Every signal, component, and function must be defined before it can be used
    • Size & type of target signal / variable must match with left-hand side
  • Concurrent Language
    • This means it is not sequential as a normal programming language
    • Allows operations to run in parallel
    • Supports different concurrent statements, instantiations, and process statements
  • Hierarchy & Partitioning
    • Supports and encourages use of hierarchy and partitioning
  • Single Pass Compiler
    • Everything must be defined before it can be used
    • Xilinx tool automatically orders files properly for analysis


There are four levels of processing that casn take place for a VHDL hardware model. They end in the Execuiton or in the synthesis.

  • Analysis ⇒ The design unit checked for syntax errors, once finalized it is stored in the Xilinx default library ⇒ xil_default
  • Elaboration ⇒ The design hierarchy is fleshed out, Unique copy of each submodule instance is created, Generics are expanded at this level
    • Execution (Vivado Simulator) ⇒ Model is simulated in discrete time step, Driven primarily by events on signals that trigger related processes
    • Synthesis (Vivado Synthesis) ⇒ A netlist description of the logic is generated either in:
      • An industry-standard or
      • A vendor specific format.

Levels of Abstractrion

  • Behavioural Level
    • Describes a system by concurrent algorithms
    • Each algorithm itself is sequential
    • Uses the higher levels of abstraction elements
    • No regard to the structural realisation of the design
sum <= a + b after 3ns;
x1: while (sum > 15) loop
end loop x1;
  • Register-Transfer Logic Level (RTL)
    • Designs using this level specify charactersitics of circuit by operations and transfer of data between registers and combinatorial logic
    • RTL design contains timing possibility of operations scheduled to ccur at certain times
sum <= a + b;
  • Gate / Structural Level
    • Characteristics of a system are described by logical links and their timing properties
    • Shows the instantiations and their connections.
inst_1: mux21 PORT MAP
        (a0 => inp1,
        a1 => inp2,
        s => sel,
        y => temp1);


Synthesis is a new addition to FPGAs, since the original inted of VHDL wad to document and simulate circuit designs

  • Synthesis
    • Process of converting the VHDL code to a collection of FPGA-specific primitives and connections
    • Primiti8ves must be physically realizable
  • Simulation
    • Runs on a comm puter
    • Many additionals abstractions and capabilites exist in the simulation envionrment; e.g., wiat for 12.031 ns;
    • Code in hardware requires a clock accuracy better than 1 THz (not achievable in today’s commercial technology)

Setting VHDL-2008 in Vivado Design Suite

For Project mode use the following command:

set_property FILE_TYPE { VHDL 2008 } [get_files <file_name>.vhd]

For Non-Project Mode use the following command

read_vhdl -vhdl2008
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