Four terminals, two flavours

A MOSFET has four terminals. The gate (G) sits on a thin insulating oxide and never conducts DC current. The source (S) is where the carriers come from, the drain (D) where they leave. The body or bulk (B) is the silicon underneath, usually tied to the source or to the supply. All voltages are measured from the source: V_GS, V_DS, V_BS. The drain current I_D is counted positive when it flows into the drain.

The pMOS is the mirror image of the nMOS: every doping type, voltage and current changes sign. Electrons in an nMOS roll down the band edge; holes in a pMOS float up. All formulas below therefore come in pairs, and you can always write the pMOS version with magnitudes: V_SG, V_SD, |V_Tp| and |I_D|.

Gate, oxide, silicon: accumulation, depletion, inversion

Now the heart of every transistor: a gate electrode (metal or heavily doped poly-silicon), a thin oxide (SiO₂: band gap ≈ 9 eV, a barrier of 3.1 eV for electrons and ≈ 4.7 eV for holes) and the p-type silicon body. No current flows through the oxide. The gate acts on the silicon only through the electric field, like one plate of a capacitor.

Raise the gate voltage V_G on p-type silicon:

• Accumulation (V_G < V_FB): the negative gate attracts holes, which pile up at the surface. Bands bend up.
• Flat band (V_G = V_FB): no charge anywhere, bands flat.
• Depletion (V_FB < V_G < V_T): holes are pushed away and leave the negative acceptor ions behind. Bands bend down. At ψ_s = φ_F, E_i crosses E_F at the surface: "mid-gap".
• Inversion (V_G > V_T): the bands bend so far that at the surface E_F is closer to E_c than to E_v. Electrons, the minority carriers, gather in a sheet a few nm thick: the surface has turned n-type. Strong inversion starts at ψ_s = 2φ_F, where the surface is as n-type as the bulk is p-type. The gate voltage there is the threshold voltage:

The silicon side is computed exactly (Poisson–Boltzmann, no depletion approximation). The field at depth where the bands are bent by ψ is

The first bracket belongs to the holes and acceptors, the second to the electrons. The surface charge is Q_s = −ε_sℰ(ψ_s), and the gate voltage splits into the work-function difference, the band bending in the silicon and the drop across the oxide: . The oxide is drawn much wider than it really is.

Interface traps

The Si/SiO₂ interface is not perfect. Broken (dangling) bonds create states inside the gap, the interface traps, with a density D_it per cm² and per eV. Like all states they are filled up to E_F. The standard picture: traps in the upper half of the gap are acceptor-like (neutral when empty, negative when filled), traps in the lower half donor-like (positive when empty, neutral when filled). In accumulation E_F sits low at the surface, so the donors between E_F and E_i are empty and positive. At mid-gap all traps are neutral. In inversion the acceptors between E_i and E_F are filled and negative. The gate must supply this trapped charge as well, so the C–V curve stretches out along the voltage axis.

Reading the C–V curve. The measured capacitance is C_ox in series with the silicon's own capacitance C_s = −dQ_s/dψ_s. In accumulation the holes respond right at the surface: C ≈ C_ox. In depletion the charge changes at the edge of a growing depletion layer: C drops. In inversion it depends on the frequency. At low frequency (quasi-static) the inversion electrons follow the signal and C climbs back to C_ox. At high frequency (~1 MHz) minority carriers cannot be generated fast enough, only the depletion edge moves, and C stays at its minimum. In the usual high-frequency picture the traps do not follow the AC signal either, but they still stretch the curve, because they take up charge whenever the DC bias changes.

A transistor is a gate-controlled barrier

Add two heavily doped n⁺ regions, source and drain, on either side of the MOS capacitor. For an electron leaving the source, the path to the drain is n⁺–p–n⁺: the p region under the gate, with its high E_c, is a barrier, like a dam. The gate controls the height of that dam.

• Off (V_GS well below V_T): the barrier is high. Only the far Boltzmann tail of the source electrons gets over. Current ≈ 0.
• Subthreshold (V_GS < V_T): the gate lowers the barrier by qΔV_GS/n (n ≈ 1.2–1.5, because part of the gate voltage drops across the oxide). The current grows exponentially, ten times for every . Because of this Boltzmann tail, no conventional transistor at room temperature can switch more steeply than 60 mV per decade.
• On (V_GS > V_T): the barrier is gone and an inversion layer, the channel, connects source and drain. For small V_DS it is a gate-controlled resistor (linear region). Once V_DS exceeds about (V_GS − V_T)/n, the channel is pinched off at the drain end and the current saturates: electrons reaching the pinch-off point roll down the steep drop into the drain like water over a weir.

Model: charge-sheet model (Brews), one formula for subthreshold, linear and saturation: I_D = μ_n(W/L)∫(−Q_i)dV along the channel, with the inversion charge Q_i from the surface-potential equation of section 2. Device: n⁺ poly gate, t_ox = 4 nm, N_A = 10¹⁸ cm⁻³, W/L = 10 µm / 1 µm, μ_n = 300 cm²/Vs, giving V_T ≈ 0.57 V. A long-channel device: short-channel effects are ignored. The band diagram follows E_c along the silicon surface; the dashed orange line is the electron quasi-Fermi level, which falls by qV_DS from source to drain.

Regions of operation and the formulas for hand calculations

The charge-sheet model of section 3 is accurate but needs a computer. For hand calculations engineers use the square-law model, with three regions. Its parameters: the process transconductance k' = μC_ox (set by the factory), the aspect ratio W/L (chosen by the designer), the threshold V_T, and the overdrive V_ov = V_GS − V_T.

• Triode (linear) region: the channel reaches from source to drain. For small V_DS it is a resistor R = 1/(k'(W/L)V_ov) whose value the gate sets.
• Saturation: the channel is pinched off at the drain end; the current depends on V_GS but hardly on V_DS. Pinch-off point moving towards the source shortens the channel a little, so the current still creeps up: channel-length modulation, λ ≈ 0.02–0.2 V⁻¹ (larger for short transistors).
• Body effect: a body below the source (V_SB > 0) widens the depletion layer, so the gate must hold more charge before inversion: with the body-effect coefficient γ = √(2qε_sN_A)/C_ox.
• Subthreshold: below V_T the current is not zero but falls exponentially, 10× per S ≈ 70–100 mV (section 3).

Check yourself: the boundary between triode and saturation is the parabola V_DS = V_GS − V_T. On the right, √I_D is a straight line in saturation; where it hits zero is the threshold voltage. That is how V_T is measured. Switch to pMOS: the same curves appear in the third quadrant, because V_DS, V_GS and I_D are all negative.

The transistor as an amplifier

For analog circuits the transistor sits at a fixed operating point (Q) and small signals ride on top. Near Q the curves are straight lines, so small changes obey linear equations:

The transconductance g_m is the slope of the transfer curve, the output resistance r_o the inverse slope of the output curve in saturation, and g_mr_o the intrinsic gain, the largest voltage gain one transistor can give. In a common-source amplifier a resistor R_D from the supply to the drain turns the current change into a voltage change: .

Increase the input amplitude: the output gets lopsided. The small-signal model is a tangent; it only holds while the swing stays small compared with the overdrive voltage.

Why switching takes time: the gate is a capacitor

To switch a transistor, its gate charge must change. The total gate capacitance is about C_oxWL, but how it is shared between source, drain and body depends on the region (Meyer model):

• Cutoff: no channel. The gate couples to the body: C_gb ≈ C_oxWL in accumulation, smaller in depletion.
• Triode: the channel touches both ends: C_gs ≈ C_gd ≈ ½C_oxWL.
• Saturation: the channel is pinched off at the drain: C_gs ≈ ⅔C_oxWL, C_gd ≈ 0.
• Plus the overlap capacitance C_ovW where the gate overlaps source and drain, and the junction capacitances of source and drain to the body (chapter 6, section 6).

In an amplifier, C_gd connects input and output. Because the output swings A_v times more than the input, C_gd looks (1 + |A_v|) times larger from the input: the Miller effect, often the main speed limit of an amplifier.

What changes when the channel is only a few dozen nanometres long

• Velocity saturation. Electron speed stops growing with the field at about v_sat ≈ 10⁷ cm/s. The saturation current then rises roughly linearly with V_ov instead of quadratically: .
• DIBL (drain-induced barrier lowering). The drain field reaches the source end of the channel and lowers the barrier of section 3: V_T drops when V_DS rises, and the off-current grows.
• Worse subthreshold swing and more leakage, because the gate loses control over the channel to source and drain.
• The cure is better electrostatics: thinner (high-k) gate dielectrics, then gates wrapped around the channel: FinFETs (gate on three sides, since 2011) and gate-all-around nanosheets (since about 2022).

Illustrative model: currents per µm of width with t_ox,eq = 1.5 nm, μ = 300 cm²/Vs, v_sat = 10⁷ cm/s; DIBL and subthreshold swing grow with an assumed exponential dependence on L. Real values depend strongly on the technology.

nMOS and pMOS formulas side by side

Next: chapter 8 puts one nMOS and one pMOS in series and gets a logic gate that uses power only while it switches.

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