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VHDL Keywords

VHDL keywords are reserved words that form the foundation of the language’s syntax and structure. They play a crucial role in defining the behavior and functionality of VHDL designs.

• Reserved words for language constructs
• Used to denote specific functions to the synthesis/compilation tool
• Cannot be used as identifiers
• Examples: architecture, entity, process, signal, variable, function, procedure, type, subtype, constant

Here’s a more comprehensive list of commonly used VHDL keywords:

VHDL Identifiers

Identifiers in VHDL are user-defined names used to uniquely identify various elements in a VHDL design. They play a crucial role in making the code readable and maintainable.

• Nouns used to describe various constructs
• Cannot be a keyword
• Names given to signals, variables, functions, procedures, and constants
• Examples: a, b, total, my_buffer
• Designers often prefer snake_case (e.g., input_signal, clock_enable)

Rules for Writing VHDL Identifiers

• Must start with a letter (a-z, A-Z)
• May contain letters, numbers (0-9), and underscores
• NO contiguous underscores are allowed
• Underscore may not end an identifier
• Case-insensitive (VHDL internally converts all characters to UPPER CASE)
• Maximum length is tool-dependent (VHDL standard supports infinite length)
• Should be descriptive and meaningful
• Avoid using abbreviations unless they are widely understood

Good identifier examples:

clock_enable
reset_counter
data_valid
address_bus
control_register

Expressions in VHDL

Expressions in VHDL are combinations of operators and operands that yield a value. They are fundamental to describing the behavior and functionality of a design.

• Similar to expressions in most high-level programming languages
• Comprises operators and operands
• Data objects (operands) and their values are used by operators
• Can be used in signal assignments, variable assignments, and conditional statements

Y <= A + (B - C);  -- operands A, B, C / operators + , -
M <= Y;            -- expression with single identifier
sig_hold <= func_or(a, b);  -- function call in an expression
result <= (a and b) or (not c);  -- boolean expression
counter <= counter + 1 when enable = '1' else counter;  -- conditional expression

VHDL Operators

VHDL provides a rich set of operators for various operations:

• Arithmetic: +, -, *, /, mod, rem, abs, **
• Relational: =, /=, <, <=, >, >=
• Logical: and, or, nand, nor, xor, xnor, not
• Shift: sll, srl, sla, sra, rol, ror
• Concatenation: &

Literals in VHDL

Literals in VHDL are constant-valued operands that represent fixed values in the code. They are essential for initializing variables, defining constants, and specifying signal values.

• Represent constant values of various data types
• Can be used directly in expressions or to initialize constants and variables
• Types include: bit, boolean, integer, real, time, string, and enumerated literals

A <= '1';              -- bit literal
Y <= "100001";         -- bit_vector literal
CH <= 'A';             -- character literal
STR <= "VHDL CLASS";   -- string literal
INT <= 35;             -- integer literal
REAL_VAL <= 3.14159;   -- real literal
TIME_VAL <= 10 ns;     -- time literal
STATE <= IDLE;         -- enumerated literal (assuming IDLE is defined in an enumerated type)
HEX_VAL <= x"FF";      -- hexadecimal literal
OCT_VAL <= o"77";      -- octal literal
BIN_VAL <= b"1010";    -- binary literal

Data Objects in VHDL

Data objects in VHDL are used to store and manipulate data within a design. They are fundamental to describing the behavior and structure of digital systems.

• Hold a value of a specific data type
• Used to pass values from one point to another
• Each can be assigned a collection of finite values

Types of Data Objects

1. Constants

• Hold only one specific value of a specific data type for a given instance
• Value cannot be changed once declared
• Improve readability of VHDL code and reduce the likelihood of errors
• Can be declared in package, entity, architecture, or process

constant MAX_COUNT : integer := 255;
constant TIMEOUT : time := 10 ns;

2. Variables

• Hold any value of a specific data type
• Used for storing temporary values inside a process, function, or procedure
• Value can be updated using a variable assignment statement (:=)
• Updated immediately when an assignment statement is executed
• Local to the process, function, or procedure where they are declared

process(clk)
  variable count : integer range 0 to 255 := 0;
begin
  if rising_edge(clk) then
    count := count + 1;
  end if;
end process;

3. Signals

• Hold a list of current and future values to be assigned
• Each signal has one or more "drivers" determining the value and timing of changes
• Each driver is a queue of events indicating when and to what value a signal is to be changed
• Signal assignments (<=) schedule events for the next simulation cycle
• Can be declared in package, entity, or architecture
• Used to model connections between components and represent actual hardware connections

signal counter : unsigned(7 downto 0) := (others => '0');
signal data_valid : std_logic := '0';

process(clk)
begin
  if rising_edge(clk) then
    counter <= counter + 1;
    if counter = 255 then
      data_valid <= '1';
    else
      data_valid <= '0';
    end if;
  end if;
end process;