Physical silicon defects such as metal shorts, broken vias, or high resistance contacts are nearly impossible to enumerate directly across millions of transistors. Automated Test Pattern Generation (ATPG) tools map physical manufacturing defects onto logical fault models so short scan patterns achieve high silicon test coverage.
Toggle inputs A, B, C and inject any stuck-at fault matching the circuit diagram in stuck_at_fault2.pdf below to see which input vectors detect the defect.
STUCK AT FAULT MODEL
The single stuck at model assumes one circuit net permanently locks to logic 0 (s@0) or logic 1 (s@1). Detecting a fault requires both controllability (driving the fault site to the opposite value) and observability (propagating that discrepancy through downstream gates to a primary output or scan flip flop).
BRIDGING, DELAY, OPEN, AND IDDQ FAULTS
- Bridging faults model unintended shorts between adjacent signal wires acting like wired AND, wired OR, or dominant aggressor logic.
- Transition delay and path delay faults capture resistive vias or slow transistors that miss clock setup deadlines even when DC logic passes.
- IDDQ quiescent supply current testing detects CMOS shorts that draw abnormal static microamp leakage during idle clock cycles.
